IEEE A-SSCC 2013 (Asian Solid-State Circuits Conference)

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Prospective authors are invited to submit full-length, four-page manuscripts, including figures, tables and references, to the official A-SSCC 2013 website. All papers will be handled and reviewed electronically. Papers are solicited in the following categories:

Regular Session

1. Analog Circuits & Systems: Amplifiers, comparators, switch capacitor circuits, continuous-time & discrete-time filters, voltage/current references; DC-DC converters, power-control circuits; IF/baseband analog circuits, AGC/VGA; display driver circuits; non-linear analog circuits.

2. Data Converters: Nyquist-rate and oversampling A/D and D/A converters, sub-circuits for data converters including sample-and-hold circuits, calibration circuits.

3. Digital Circuits & Systems: Design, fabrication, and test of digital VLSI systems; high-speed low-power digital circuits, power-reduction and management methods for digital VLSI, leakage reduction techniques; clock distribution, I/O circuits, reconfigurable logic-array circuits; supply/substrate noise measurement and cancellation for digital VLSI, variation and fault-tolerant circuits.

4. SoC & Signal Processing Systems: System-on-chip, microprocessors, network processors, baseband communication processing system & architectures, low-power signal-processing systems; multimedia processors including video, image, audio and voice processing systems; cryptographic and security-processing circuits and systems; bio-medical/neural signal processors.

5. RF: Receivers/transmitters/transceivers for wireless systems; narrowband RF, ultra-wideband and millimeter-wave circuits; circuits and sub-circuits for RF front-end, LNA, mixer, power amplifiers, VCOs, frequency synthesizers, RF filters, RF switches, power detectors, active antennas.

6. Wireline & Mixed-Signal Circuits: Receivers/transmitters/transceivers for wireline systems including (but not limited to) LAN, WAN, FDDI, Ethernet, token-ring, fiber channel, SONET, SDH, PON, ATM, ISDN, xDSL, cable-modem; optical/electrical data links and backplane transceivers; power-line communication; clock generation circuits, PLL, DLL, spread-spectrum clock generation.

7. Emerging Technologies and Applications: Advanced circuit technologies and techniques; ultra-low-voltage and sub-threshold logic design; molecular-, organic-, and nano-electronics; flexible substrates and printable electronics; 3D-integration and novel packaging technologies; compound-semiconductor, superconductive, and micro-photonic technologies and circuits; energy sources and energy harvesting; ambient-intelligence; emerging applications and circuits; medical/bio-electronics/bio-inspired chip design; RFID; analog and optical processors, non-transistor-based analog and digital circuits and systems; advanced memory technologies; spintronics; quantum storage.

8. Memory: Static, dynamic, non-volatile, read-only memory; magnetic and ferro-electric memory design and architecture; data storage and multi-bit-cell-based memory design; embedded memory architecture, cache-memory system, multi-port memory, and CAM design, nano-crystal, phase-change, and 3D memories; yield-enhancement redundancy and ECC techniques; memory testing and built-in self-test.

Special Session

1. Industry Program: This special category accepts only papers based on state-of-the-art products. The paper may cover specifications, applications, state-of-the-art points, chip photos, chip architecture/software, circuits (not necessarily very original, significant improvement is fine), live demo if any, characterization results, and packaging/testing results.

2. Student Design Contest: A student design contest is held among the accepted papers with system prototypes or measurement results of which operations can be demonstrated on-site.

Papers on low-power and/or low-voltage approaches, signal integrity, noise, test, and manufacturability for all the above categories are welcomed. Measurement results are highly recommended, especially for analog, and RF categories. Design methodologies for SiP, SoC, interconnections and statistical design are included in the scope of the conference; the papers only describing CAD tools and CAD algorithms are not considered. Dual submission to other conferences is not allowed. A special issue of the IEEE Journal of Solid-State Circuits will be prepared for publication of the outstanding papers of this conference.


 Paper submission deadline  June 12, 2013, 20:00 (GMT)
 June 22, 2013,20:00 (GMT)
 Acceptance notification  August 19, 2013
 Deadline for final paper submission September 16, 2013
 Conference 11 to 13 November 2013

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